Optimal Zero-Aliasing Space Compaction of Test Responses

Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The effectiveness of such a compaction method can be measured by its compaction ratio c = k/q. A high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the faultfree signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio cmax. We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. Given a circuit under test, a fault model, and a test set, we determine qmin, which yields cmax = k/qmin. This provides a fundamental bound on the cost of signature-based BIST. We show that qmin ‹ 2 for all the ISCAS 85 benchmark circuits. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS 85 circuits. Finally, we describe multistep compaction, which allows zero aliasing to be achieved with any q, even